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SiC714CD10
New Product
Vishay Siliconix
Fast Switching MOSFETs With Integrated Driver
PRODUCT SUMMARY
Input Voltage Range Output Voltage Range Operating Frequency Continuous Output Current Peak Efficiency Optimized Duty Cycle Ratio 3.3 to 15 V 0.5 to 6 V 100 kHz to 1 MHz Up to 27 A 94% at 300 kHz 10%
FEATURES
D D D D D D Low-side MOSFET control pin for pre-bias start-up Undervoltage Lockout for safe operation Internal boostrap diode reduces component count Break-Before-Make operation Turn-on/Turn-off Capability Compatible with any single or multi-phase PWM controller D Low profile, thermally enhanced PowerPAKr MLF 10 x 10 Package
PowerPAKr MLF 10 x10
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APPLICATIONS
D DC-to-DC Point-of-Load Converters - 3.3 V, 5 V, or 12-V Intermediate BUS - Examples - 12 VIN / 0.8 - 2.5 VOUT - 5 VIN / 0.8 - 1.5 VOUT D Servers and Computers D Single and Multi-Phase Conversion
Bottom View Ordering Information: SiC714CD10-T1 (with tape and reel)
DESCRIPTION
The SiC714CD10 is an integrated solution which contains two PWM-optimized MOSFETs (high side and low side MOSFETs) and a driver IC. Integrating the driver allows better optimization of Power MOSFETs. This minimizes the losses and provides better performance at higher frequency. The SIC714CD10 is packaged in Vishay Siliconix's high performance PowerPAK MLF 10x10 package. Compact copackaging of components helps to reduce stray inductance, and hence increase efficiency.
FUNCTIONAL BLOCK DIAGRAM
VDD
CBOOT VIN UVLO
SHDN
+ -
BBM SW
VDD PWM SYNC CGND
PGND
Figure1
Document Number: 73569 S-52308--Rev. A, 31-Oct-05 www.vishay.com
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SiC714CD10
Vishay Siliconix
New Product
ABSOLUTE MAXIMUM RATINGS (TA = 25_C UNLESS OTHERWISE NOTED)
Parameter
Logic Supply Logic Inputs Drain Voltage Bootstrap Voltage Maximum Power Dissipation (Measured at 25_C) Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature)a, b
Symbol
VDD VPWM VIN VBOOT PD Tj, Tstg
Steady State
7 7.3
Unit
V 20 SW+ 7 6 -65 to 125 260 W _C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Drain Voltage Logic Supply Input Logic PWM Voltage Bootstrap Capacitor
Symbol
VIN VDD VPWM CBOOT
Steady State
3.0 to 15 4.5 to 5.5 5 100 n to 1 m
Unit
V
F
THERMAL RESISTANCE RATINGS
Parameterc
Maximum Junction-to-Case Maximum Junction-to-Ambient (PCB = Copper 25 mm x 25 mm) Steady State
Symbol
RthJC RthJA
Typical
2.1 50
Maximum
2.6 75
Unit
_C/W
Notes a. See Reliability Manual for profile. The PowerPAK MLF 10 10 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. b. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. c. Junction-to-case thermal impedance represents the effective thermal impedance of all heat carrying leads in parallel and is intended for use in conjunction with the thermal impedance of the PC board pads to ambient (RthJA = RthJC + RthPCB-A). It can also be used to estimate chip temperature if power dissipation and the lead temperature of a heat carrying (drain) lead is known.
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Document Number: 73569 S-52308--Rev. A, 31-Oct-05
SiC714CD10
New Product
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified Parameter Power Supplies
Logic Voltage Logic Current (Static) VDD IDD(EN) IDD(DIS) IDD1(DYN) Logic Current (Dynamic) IDD2(DYN) VDD = 4.5 V, SYNC = H, PWM = H, SHDN = H VDD = 4.5 V, SYNC = H, PWM = H, SHDN = L VDD = 5 V, fclk = 250 kHzc VDD = 5 V, fclk = 0.7 MHzc 4.5 1166 120 27.5 59.5 mA 5.5 V mA
Limits Min Typa Max Unit
Symbol
TA = 25_C 4.5 V < VDD < 5.5 V, 4.5 V < VD1 <20 V
Logic Input
High Logic Input Voltage (VPWM) Low Logic Input Voltage (VSYNC) Logic Input Voltage (VSHDN) Input Voltage Hysteresis (PWM) Logic Input Current VPWMH VPWML VSYNC VSHDN VHYS ISHDN IPWM VDD = 5.5 V, SHDN = 0 V VDD = 5.5 V, PWM = 5.5 V 2.5 VDD = 5 V, SYNC = H, SHDN = H V H VDD = 5 V, PWM = H, SHDN = H VDD = 5 V, PWM = H, SYNC = H 2.0 2.0 400 117 120 mV mA 1.35 V
Protection
Break-Before-Make Reference Under-Voltage Lockout Under-Voltage Lockout Hysteresis VBBM VUVLO VH VDD = 5 V SYNC = H SHDN = H V, H, VDD = 5.5 V 3.5 2.4 4 0.4 4.25 V
MOSFETs
Drain-Source Voltage Drain-Source On-State Drain Source On State Resistancea VDS rDS(on)1 rDS(on)2 VSD1 VSD2 IS = 2 A, VGS = 0 V A ID = 250 mA VDD = 5 V, ID = 10 A TA = 25_C High-Side Low-Side High-Side Low-Side 20 22 10.2 3 0.7 0.67 12.75 3.6 1.1 1.1 V mW V
Diode Forward Voltagea
Dynamicb, c
Turn On Delay Time Turn Off Delay Time td(on) td(off) 66 50%--50% 50% 50%c 32 ns
Notes a. Pulse test: pulse width v300 ms, duty cycle v2%. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. Using application board SiDB766707.
Document Number: 73569 S-52308--Rev. A, 31-Oct-05
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SiC714CD10
Vishay Siliconix
TIMING DIAGRAM
New Product
SHDN SYNC PWM HS MOSFET Gate LS MOSFET Gate SW td(on) td(off)
Figure 2
APPLICATION INFORMATIONa (25_C UNLESS NOTED, LFM = 0)
Total Efficiency 12 VIN/2.5 VOUT
94 92 90 5 Total Loss (W) Efficiency (%) 88 86 84 82 80 1 78 76 0 10 Output Current - (A) 20 0 0 5 10 15 20 25 Output Current - (A) 4 3 2 7 6
Total Loss 12 VIN/2.5 VOUT
-- 700 kHz
300 kHz
-- 700 kHz
300 kHz
Figure 3
Figure 4
Notes a. Experimental results using an evaluation board with a specific set of operating conditions. www.vishay.com Document Number: 73569 S-52308--Rev. A, 31-Oct-05
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SiC714CD10
New Product
PIN CONFIGURATION
PowerPAK MLF 10 mm
SW SW SW SW SW SW SW SW SW
Vishay Siliconix
10 mm (Bottom View)
VIN VIN VIN VIN VIN VIN VIN NC 61
52
53
54
55
56
57
58
59
60
62
63
64
65
66
67
PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 (SW) CGND Driver Tab Low-Side MOS Tab VIN High-Side MOS Tab
68
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
VIN VIN VIN VIN VIN VIN VIN VIN VIN NC CGND CBOOT NC CBOOT VDD NC NC
34 NC
33 NC
32 NC
31 NC
30 NC
TRUTH TABLE
SHDN
L H H H H
29 NC
28 SHDN
27 SYNC
26 PGND
25 NC
24 CGND
23 PWM
22 NC
21
20 NC
19
18
VDD
VDD
NC
SYNC
X L L H H
PWM
X L H L H
HS MOSFET
OFF OFF ON OFF ON
LS MOSFET
OFF OFF OFF ON OFF
PIN DESCRIPTION
Pin
1-9, 62-68 10, 13, 16-18, 20, 22, 25, 29-34, 61 11, 24 12, 14 15, 19, 21 23 27 28 26, 35-51 52-60 Document Number: 73569 S-52308--Rev. A, 31-Oct-05
Symbol
VIN NC CGND CBOOT VDD PWM SYNC SHDN PGND SW No Connect
Description
Input Voltage (High-Side MOSFET Drain)
Control Ground. Should be connected to PGND externally Connection pin for Bootstrap Capacitor for Upper MOSFET Logic Supply Voltage--decoupling to GND with a CAP is strongly recommended Pulse Width Modulation (PWM) Signal Input Disable Low-Side MOSFET Drive Disable All Functions (Active Low) Power Ground (Low-Side MOSFET Source) Connection Pin for Output Inductor (High-Side MOSFET Source/Low-Side MOSFET Drain) www.vishay.com
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SiC714CD10
Vishay Siliconix
DEVICE OPERATION Pulse Width Modulator (PWM)
This is a CMOS compatible logic input that receives the drive signals from the controller circuit. The PWM signal drives the buck switch.
New Product
SYNC Pin for Pre-Bias Start-Up
The low side MOSFET can be individually enable or disabled by using the SYNC pin. In the low state (SYNC = low), the low-side MOSFET is turned off. In the high state, the low-side MOSFET is enabled and follows the PWM input signal (see timing diagram, Figure 2). SYNC is a CMOS compatible logic input and is used for a pre-biased output voltage.
Break Before Make (BBM)
The SiC714CD10 has an internal break-before-make function to ensure that both high-side and low-side MOSFETs are not turned on at the same time. The low-side MOSFET will not turn on until the high-side gate drive voltage is less than VBBM, thus ensuring that the high-side MOSFET is turned off. This parameter is not user adjustable.
Voltage Input (VIN)
This is the power input to the drain of the high-side Power MOSFET. This pin is connected to the high power intermediate BUS rail.
SHDN
CMOS logic signal. In the low state, the SHDN disables both high-side and low-side MOSFET's.
Switch Node (SW)
The Switch node is the circuit PWM regulated output. This is the output applied to the filter circuit to deliver the regulated high current output for thebuck converter.
Capacitor to Boot Input (CBOOT)
Connected to VDD by an internal diode via the CBOOT pin, the boot capacitor is used to sustain a voltage rail for the high-side MOSFET gate drive circuit.
Power Ground (PGND)
This is the output connection from the source of the low-side MOSFET . This output is the ground return loop for the power rail. It should be externally connected to CGND.
Under Voltage Lockout (UVLO)
During the start up cycle, the UVLO disables the gate drive holding high-side and low-side MOSFET's low until the input voltage rail has reached a point at which the logic circuitry can be safely activated. The UVLO is not user adjustable.
Control Ground (CGND)
This is the control voltage return path for the driver and logic input circuitry to the SiC714CD10. This should externally connected to PGND.
APPLICATION CIRCUIT
3.3 V to 16 V
Power Up Sequence: The presence of VDD prior to applying the VIN and PWM is recommended to ensure a safe turn on Power Down Sequence: The sequence should be reverse of the on sequence, turn off the VIN before turning off the VDD.
5V
VDD
CBOOT VIN Q1 SW CBOOT L VOUT + LS Q2 PGND PGND
HS SYNC DC-DC Controller PWM SHDN CGND CGND MOSFET Drive Circuitry with Break-BeforeMake
Figure 7
The SiC714CD10 has a built-in delay time that is optimized for the MOSFET pair. When the PWM signal goes low, the high-side driver will turn off, after circuit delay (tdoff ), and the output will start to ramp down,( tf ). After a further delay, the low-side driver turns on.
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When the PWM goes high, the low-side driver turns off,( tdon ). As the body diode starts to conduct, the high-side MOSFET turns on after a short delay . The delay is minimized to limit body diode conduction. The output then ramps up,(tr ).
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Document Number: 73569 S-52308--Rev. A, 31-Oct-05
SiC714CD10
New Product
TYPICAL APPLICATION
12 V 5V
Vishay Siliconix
VDD SYNC SHDN PWM CGND
VIN
CBOOT SW PGND
SiC714CD10
VDD SYNC PWM1 PWM Control Circuit PWM2 PWM3 PWM4 SHDN PWM CGND
VIN
CBOOT SW PGND
SiC714CD10
VOUT
VDD SYNC SHDN PWM CGND
VIN
CBOOT SW PGND
SiC714CD10
VDD SYNC SHDN PWM CGND
VIN
CBOOT SW PGND
SiC714CD10
Figure 8
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?73569. Document Number: 73569 S-52308--Rev. A, 31-Oct-05 www.vishay.com
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Legal Disclaimer Notice
Vishay
Notice
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale.
Document Number: 91000 Revision: 08-Apr-05
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